Two-Leg Neutral-Point Diode-Clamped Active Front-End Rectifier

Active front-end boost rectifiers can replace the uncontrolled diode bridge rectifiers for ac–dc conversion offering high power quality with near unity power factor. The four-switch, B4, topology is gaining interest, either as an inverter or a rectifier, where each switch should withstand the full dc-link voltage. Higher voltage-rated power semiconductor devices not only imply slower response with lower overall efficiency but also higher cost and size. Thus, multilevel inverters become a viable solution. This article investigates a two-leg neutral-point diode-clamped B8 rectifier allowing the series connection of fast, efficient, and low voltage-rating switches. The proposed rectifier has a better performance and efficiency than the B4 rectifier. Only two inductors instead of three are required. Model predictive current control (MPCC) is developed for accurate current tracking. A model of the proposed rectifier is detailed for the implementation of MPCC. The concept is validated by simulation and experimentation.


I. INTRODUCTION
A DJUSTABLE speed drives (ASDs) with higher power and voltage levels have gained attention in the industrial section.They offer better efficiency by adjusting the speed and torque depending on the load demand and can operate with partial instead of full load power [1].ASDs are based on twostage conversion, where the first stage is ac-dc conversion and the second stage is dc-ac conversion with controllable voltage and frequency (see Fig. 1).
Conventionally, uncontrolled diode bridge rectifiers are used for the ac-dc conversion stage.However, the high harmonic content (which depends on the load and could reach 100%, see Fig. 2, where THD stands for the total harmonic distortion), distorted supply current, low efficiency, and low power factor are major concerns, particularly with growing interest in power quality [2].
Passive filters, which are a combination of inductors and capacitors, were conventionally used to attenuate harmonic pollution [5].However, they are only efficient in eliminating certain harmonics previously tuned for.Their interaction with the connected load can cause resonance problems.
Conversely, APFs are more flexible and have excellent filtering performance [6].Shunt APF (SAPF) is a current-controlled voltage source inverter with a dc capacitor and three interfacing filter inductors.It acts as a current source feeding the harmonic content and reactive power to the load, thus resulting in a pure sinusoidal supply current in phase with the voltage.However, the SAPF rating may be as high as the load rating.Therefore, high cost and high losses, along with a complex control algorithm for harmonic content extraction [7] and reference current generation, limit its deployment.
Generally, filters (either passive or active) are suitable for existing electrical installations.However, for future installations, it is recommended to alter the design of the ac-dc converter to cope with stringent power quality regulations.
Multipulse transformer-based rectifiers, such as 12, 18, and 24 pulses rectifiers, can reduce the THD [8].It is reported that THD is in the range of 15% using a 12-pulse rectifier [9].However, its bulky structure makes it a less favorable choice.
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APFCs are unidirectional two-stage ac-dc converters, where the first stage is a traditional three-phase uncontrolled diode bridge rectifier followed by a dc-dc boost converter for power factor correction [10].The converter uses a single switch.However, THD is still in the range of 25%-30% [11].
AFERs are conventional voltage source converters offering bidirectional power flow [12].This allows ac-dc conversion in the motoring mode, while dc-ac conversion takes place in regenerative braking mode (pumping back the energy to the grid increasing drive efficiency).Also, AFER allows regulation of the dc-link voltage [13].Control of the AFER power switches allows the shaping of the current into a sinusoidal waveform in phase with the voltage, resulting in near unity power factor with low THD (<5%).With all these mentioned merits, AFERs are regarded as an excellent solution for power quality concerns associated with ac-dc conversion in ASDs [14].
AFER control has been a popular topic in recent years [15].In [16], a quasi-resonant extended state observer-based predictive current control strategy has been proposed to achieve robust control against system parameter variations.To improve the AFER dynamic response, a predictive short-horizon control approach is proposed in [17].In [18], finite-time adaptive fuzzy control is proposed to improve the AFER performance, where the control approach estimates and compensates for load disturbances and system uncertainties.A fractional-order linear active disturbance rejection controller is discussed in [19] replacing the conventional proportional-integral (PI) controller, thus enhancing the current tracking performance.In [20], a voltage-sensorless predictive current controller is presented to improve the AFER accuracy and dynamic response.
Generally, the six-switch (B6) rectifier is an intuitive selection.However, for the same output dc-link voltage, the four-switch (B4) rectifier has the merit of lower conduction and switching losses as one of the inverter legs is replaced with a split dc capacitor [21].Hence, the B4 rectifier has been widely investigated in the literature with several techniques for balancing the dc-side capacitor voltages [22], [23], [24].However, in the B4 rectifier, as well as the B6 rectifier, the switch must withstand the full dc-link voltage.Thus, high voltage-rated power semiconductor devices are required, which not only imply slower response with lower overall efficiency but also higher cost and footprint [25].Consequently, multilevel converters, especially the neutral-point diode-clamped converter (NPC), become a viable solution [26].Typically, multilevel converters are used in mediumvoltage high-power applications [27].They have the advantage of higher voltage ratings with lower device stresses with the inherited lower harmonics [28].
This article investigates a two-leg, eight-switch (B8) [29], [30] neutral-point diode-clamped rectifier, which allows a series connection of fast, efficient, and low voltage switches.The proposed rectifier has a better performance and efficiency than the B4 rectifier.In addition, only two boost inductors instead of three are required.A finite control set model predictive current control (FCS-MPCC) approach is deployed instead of conventional control approaches.Hence, better current tracking performance is achieved and the cost function is easily modified to account for the dc-link capacitor voltage balancing.This article's contribution is as follows.
1) An eight-switch AFER is proposed, which allows the utilization of fast, efficient, and low voltage-rating devices, resulting in lower converter losses and THD.
2) The proposed rectifier requires only two boost inductors.
3) An FCS-MPCC approach, accounting for two-inductor topology instead of three, is proposed for better current tracking.
This article is organized as follows.Section II discusses the proposed rectifier highlighting the basic principles along with detailed mathematical modeling of the proposed rectifier.The concept of FCS-MPCC applied to the B8, two-inductor, rectifier is investigated in Section III.Section IV addresses the problem of dc-side capacitor imbalance.Simulation results of the proposed control approach are illustrated in Section V. A performance comparison of the proposed B8 rectifier with the B4 rectifier with advanced control techniques is given in Section VI, while Section VII gives a comprehensive comparison between the proposed B8 and the conventional B4 rectifier regarding efficiency and device rating.Experimental results, validating the proposed concept, are given in Section VIII.

II. PROPOSED B8 RECTIFIER
This section demonstrates the proposed two-leg eight-switch (B8) NPC, two-inductor, and rectifier.Reference current generation is briefly highlighted followed by a detailed mathematical model of the proposed rectifier.Fig. 3 shows the proposed topology comprised of eight switches along with four clamping diodes.Any arbitrary phase, for example, Phase "a" is connected to the center point of the split dc-side capacitor.Only two boost inductors, L f , are deployed instead of the three used in conventional topologies.

A. Reference Current Generation
The AFER aims to achieve three-phase pure sinusoidal grid currents in phase with the three-phase voltages, thus improving the power factor (near unity) and reducing the harmonic content.Therefore, the three reference currents' waveforms are known (identical to the grid sinusoidal voltage waves), leaving the only unknown to be the magnitudes.
Since the load is fed from the split dc-link capacitor, the variation in the magnitude of the dc-side capacitor is related to the magnitude of the supply current.Fig. 4 shows the process of reference current generation [31].
A scaling circuit (phase-locked loop to extract the frequency and angle of the supply voltage followed by a three-phase unity-magnitude signal) is employed to generate three template reference waveforms with unity magnitude in phase with the three-phase supply voltages.The split dc-link capacitor voltage is compared with a reference value, where the error signal is processed by a PI controller generating the magnitude of the reference currents.Finally, the magnitude of the reference currents is multiplied by the template sinusoidal waveforms  generating the required three-phase reference currents (which are in phase with the voltage and with a magnitude depending on the load).

B. Modeling of the Proposed B8, Two-Inductor, Rectifier
For accurate reference current tracking, a mathematical model of the proposed B8 rectifier is required.Referring to Fig. 3, the converter voltages with respect to the converter reference, O, are described by where v c1 , and v c2 are the upper and lower capacitor voltages, respectively, and s b1 , s b2 , s c1 , and s c2 are the two upper switches of phases b and c (1 represents that the switch is on and 0 represents that the switch is off).The switches s x1 and s x3 , and s x2 and s x4 (with x representing either phase b or c) are complementary, so it is sufficient to describe the voltage state of any phase with only the two upper switches.For each phase, three different voltage states are available (resulting in nine different cases) according to the state of the switches, as summarized in Table I.
The converter voltages with respect to the grid neutral, n, are given by

TABLE I SWITCHING STATES AND CORRESPONDING VOLTAGES
Adding the three components of (2), knowing that for a balanced three-phase system (3) holds e an + e bn + e cn = 0 Hence, the potential difference between the grid neutral, n, and the converter reference, O, is defined by Combining ( 1), (2), and (4), the continuous-time model of the converter is then defined by (5) Currents in the upper and the lower dc-side capacitors are defined by the switching states along with the rectifier currents as given by where C is the capacitance of each capacitor and V 1 and V 2 are the initial voltages on the upper and lower capacitors, respectively.

III. FINITE CONTROL SET MPCC
The popular current controllers are the hysteresis band current controller (HBCC), the linear pulsewidth modulation (PWM), and the deadbeat (DB) current control techniques [32].Hysteresis control is a nonlinear current control approach where the error in current is handled by a hysteresis band controller.The state of the switch changes when the error goes outside a predefined band.Usually, a narrow hysteresis band is selected to guarantee accurate current tracking resulting in a high nonuniform switching frequency.
PWM is a linear control approach, which uses a PI controller to generate the reference voltage signals.Then, a modulating stage is required, either through carrier triangular waveforms or space vector modulation (SVM), to generate the required gating signals.However, PI control in the stationary reference frame results in an unsatisfactory, slow response with poor tracking capability [33].
PI control could be replaced with DB control, which generates the required voltage vector resulting in zero current error in the next sampling instant.However, DB control is sensitive to system parameter variation, noise in the measured signals, and calculation delay requiring a high sampling frequency [34].
The salient disadvantages of classical current control approaches fueled the need for finding an advanced approach, which overcomes the mentioned shortcomings.FCS-MPCC emerged as an excellent current control approach [35].FCS-MPCC has a different strategy, where all the possible future behaviors are predicted based on a discrete-time model of the plant, and then, the optimal control action (which minimizes the predefined cost function in the next sampling instant) is selected [36].Hence, it is a proactive approach where a decision is taken before the error in current occurs.As opposed to PWM and DB control techniques, FCS-MPCC does not require a modulating stage.Also, it offers better transient and steady-state performances compared with classical control approaches.Finally, FCS-MPCC can incorporate constraints in the cost function (voltage balancing of split dc capacitor for example), hence satisfying multiobjective control targets [37].Model predictive current control (MPCC) covers a wide range of power converter applications [38].
A comprehensive comparison between FCS-MPCC and popular current control approaches, namely, linear PWM, HBCC, and DB, is given in Table II.
Since FCS-MPCC requires a plant discrete-time model, the first-order continuous-time model of the rectifier, described in Section II, is discretized using Euler's method defined by where T s is the sampling time.
Then, the predicted rectifier currents (defined in continuous time by (5) in Section II) are given by (9) in the discrete-time domain at sample (k + 1) where y represents the phase (a, b, and c) and V y is the voltage for each phase, defined by The voltages depend on the switching states along with the split dc-link capacitor voltages and the grid voltages.Table III summarizes the voltages for the nine possible switching states.
FCS-MPCC has five steps.1) Extrapolating the reference current using the Lagrange method defined by where y represents the phase (a, b, and c).
2) Measuring the rectifier currents i a (k), i b (k), and i c (k).In a balanced three-phase system, it is sufficient to measure only two currents and detect the third.3) Calculating all the possible voltages using Table III.
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TABLE III SWITCHING STATES AND CORRESPONDING VOLTAGES
4) Calculate the predicted rectifier currents defined by (9).5) Evaluate the cost function given by (12), which represents the absolute error between the reference current and the predicted current The switching state, which minimizes the cost function, is selected and applied to the converter.Fig. 5 summarizes and illustrates the operation of FCS-MPCC.

IV. BALANCING OF DC-SIDE CAPACITOR VOLTAGES
In the B8 configuration either operating as an inverter, rectifier, or SAPF (as well as the B4 configuration), one of the three phases is connected to the midpoint of the split dc-link capacitor.This connection results in an imbalance with the capacitor voltages.If this imbalance is not resolved, the converter will not operate properly.In addition, unequal capacitor voltages result in unequal voltage stress on the switching devices, which may lead to converter failure.
An advantage of FCS-MPCC is the possibility of handling multiobjectives, where the primary objective is current control, while the secondary objective is capacitor voltage balancing.Each objective defined in the cost function is multiplied by a weighting factor reflecting its importance.
To balance the dc-side capacitor voltages, the discrete-time model of the capacitor voltages and currents must be defined.
The dc-side capacitor currents are defined by The predicted capacitor voltages are given by Hence, the cost function is modified to account for capacitor imbalance as defined by the following equation: where λ i and λ v represent the weighting factors for current and voltage balancing, respectively.
Changing the values of weighting factors offers flexibility, resulting in adjustable performance, that is, if λ v is set to zero, the cost function will become a single objective with current control only, without considering the capacitor voltage imbalance.On the other hand, setting a nonzero value of λ v will introduce a secondary objective in the cost function.Several methods are available for selecting the weighting factors, such as the heuristic approach, per unit method, and lookup table [39].Using (15), the switching state, which ensures optimal current tracking and balancing the capacitor voltages, is selected.

V. SIMULATION RESULTS
In this section, the simulation results of the proposed B8, two-inductor, rectifier are presented and compared against the B4 rectifier (with only two boost inductors).
The B8 rectifier current is controlled using FCS-MPCC.On the other hand, conventional HBCC is deployed for the B4 rectifier.
Table IV shows the parameters used for the simulation.A hysteresis band of 2A is selected to improve the performance of the HBCC for a valid comparison.Fig. 6 shows the performance comparison between the two approaches.
Fig. 6(a) shows the three-phase grid currents for both approaches, where a balanced three-phase sinusoidal waveform is obtained.

(b) shows phase
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply."a" reference current along with the actual current for both approaches, where the current follows the reference.
Fig. 6(c) shows the single-phase voltage and current waveforms, where both waveforms are in phase yielding unity power factor.Fig. 6(d) shows the split dc capacitor voltages, where the proposed B8 rectifier has better voltage balancing due to the flexibility of FCS-MPCC to include constraints in the cost function.Finally, the switch voltage stress for both approaches is shown in Fig. 6(e).Each switch in the proposed B8 rectifier should withstand only half the dc-link voltage as opposed to the B4 rectifier, where the switches should withstand the full dc-link voltage.Also, Fig. 6(e) shows that with the same sampling time (20 µs), both approaches have nearly the same average switching frequency (around 8 kHz).Fig. 7 shows the dynamic performance of the proposed B8 rectifier and the B4 rectifier when the load changes.Both rectifiers cope with the dynamic change, maintaining sinusoidal current waveforms, as shown in Fig. 7(a).However, only the proposed B8 rectifier manages to balance the split dc-capacitor voltages before and after the load change, as shown in Fig. 7(b).This reflects the superiority of the proposed B8 rectifier, which includes the capacitor voltage balancing in the cost function.
To further explore the performance of the proposed B8 rectifier, two cases are considered: the first case is an unbalanced grid voltage and the second case is a distorted grid voltage.Results for both cases are shown in Fig. 8.
For the unbalanced grid voltage case, a 25% unbalance in both phase and magnitude is studied, where the magnitude of phase "a" is 1.25 × the rated voltage magnitude.Also, phase "a" is advanced by 30 o (25% of the normal 120 o phase shift), as shown in Fig. 8(a)-Case 1. Next, a 25% distortion in grid voltage is simulated by injecting a third harmonic component as in Fig. 8(a)-Case 2.
Generally, as per Fig. 4, the grid current is in phase with the grid voltage for balanced/undistorted grid voltage conditions.However, when unbalance/distortion is introduced to the grid voltage, the scaling circuit, in Fig. 4, extracts the positive sequence component of the grid voltage generating the required unit template reference current as shown in Fig. 8(b) for both cases.Examining both parts of Fig. 8(b) reveals a difference in phase shift between the unit template reference currents in both cases.This is expected as Case 1 studies the unbalanced grid voltage condition, while Case 2 shows distorted grid voltage, with balanced grid voltages.
Balanced, sinusoidal three-phase grid current is achieved as shown in Fig. 8(c), with 3.03% and 2.21% THD for the unbalanced and distorted grid voltage cases, respectively.Fig. 8(d) shows a balanced split dc-link capacitor voltage in both cases.

VI. PERFORMANCE COMPARISON OF THE PROPOSED B8
RECTIFIER AND CONVENTIONAL B4 RECTIFIER OPERATING WITH ADVANCED CONTROL TECHNIQUES Sections VI-A and VI-B demonstrated the performance of the proposed B8, two-inductor rectifier using FCS-MPCC.Its performance was compared against a B4, two-inductor rectifier controlled by conventional HBCC.
The proposed converter, which allows a series connection of switches, showed superior performance as a three-level operation was achieved instead of two-level operation of the B4 rectifier.
This section further compares the proposed B8, twoinductor rectifier using the proposed modified FCS-MPCC against the conventional B4 three-inductor rectifier, operated with advanced control techniques namely: a DB predictive current controller and MPCC, which are briefly highlighted in the following subsection.

A. DB Predictive Current Controller
The DB control is a predicative-type controller where the optimal reference voltage resulting in zero current error in the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.discrete-time domain where y represents the phase (a, b, or c), i(k + 1) * y is the required reference current in the next sample (k+ 1), and i(k) y is the actual current at sample k.Note that the DB controller followed by an SVM stage will not be possible if only two Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.inductors are utilized as the voltages will not be balanced.In this case, sinusoidal PWM can be utilized.

B. Model Predictive Current Controller
The concept and advantages of MPCC are covered in Section III.This section provides the essential equations for the mathematical modeling of the B4, three-inductor rectifier.
The predicted rectifier currents (as per Section III) are given by ( 9) in the discrete-time domain at sample (k+ 1).
For the B4 rectifier with three inductors, the phase voltage V y is defined by Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE V THD FOR THE PROPOSED B8 AND THE CONVENTIONAL B4 RECTIFIER
where s b and s c are the upper switches of phases b and c, respectively.Fig. 9 shows the results of the B4, three-inductor rectifier controlled by DB and MPCC, with the parameters in Table IV and with an 8-kHz average switching frequency.The 5.01% and 4.47% THD are recorded for the DB and the MPCC, respectively, as shown in Fig. 9(a).Balanced split dc-side capacitor voltages are shown in Fig. 9(b).Although, the performance of the conventional B4, three-inductor rectifier controlled by DB and MPCC is better than the performance of the B4 two-inductor rectifier controlled with HBCC.However, the performance of the proposed B8, two-inductor rectifier with FCS-MPCC, exceeds the performance of the B4 rectifier, either with two or three inductors with any control approach, revealing the advantage of three-level operation.THD results are summarized in Table V.

VII. COMPARISON OF THE PROPOSED B8 RECTIFIER AND CONVENTIONAL B4 RECTIFIER
For a complete comparison between the proposed B8, twoinductor rectifier, and the conventional B4, three-inductor rectifier, the switching losses and conduction losses of the two rectifiers must be assessed [40], [41].Table VI shows the main specifications of the utilized power switches.The switches are from the same company (IXYZ) for a fair comparison.
The power MOSFET conduction loss can be calculated using a drain-source ON-state resistance R DSon , which is obtained using the datasheet, as per Table VI.The B8 rectifier utilizes double the switch number of the B4 rectifier, and however, the lower voltage-rating semiconductor devices have lower ON-state resistance.The ratio between conduction losses of the B8 rectifier and the B4 rectifier, for the same load, is defined by (18), which shows a 14% reduction in conduction losses for the B8 rectifier, as lower voltage-rating devices are deployed Switching losses arise during the switch turn on/off, where the losses depend on the drain-source voltage (V DS ), load current (I D ), and the turn on/off times (T on and T off , respectively).(Losses in clamping diodes could be neglected as fast Schottky devices are deployed.)Equation ( 19) defines the switching losses assuming a linear voltage/current switching behavior where f s is the switching frequency.
For the same switching frequency and load current, the ratio of switching losses for the B8 and the B4 rectifiers is defined by (20), showing a 59% reduction in switching losses as fast and low voltage-rating devices are used in the B8 rectifier The proposed topology utilizes lower voltage-rating semiconductor devices, which have the merits as follows: 1) lower cost; 2) smaller size; 3) higher efficiency; 4) faster response.
The proposed topology adds minimal cost to the converter (extra gate drivers and clamping diodes) when compared with the conventional B4 rectifier.Conventionally, VA is used as a measure to compare the power ratings of semiconductor devices.Since the proposed topology allows series switch connection, each switch is chosen to withstand only half the dc-link voltage, with the same current rating.Although the number of switches increases in the proposed topology, the overall VA does not change.The clamping diodes are additional components.The voltage rating of the clamping diodes is half the dc-link voltage.Table VII summarizes the comparison between the B4 and the proposed B8 rectifier.

VIII. EXPERIMENTAL RESULTS
The experimental results of the proposed B8 rectifier are presented in this section.The experimental test rig used to confirm the findings is shown in the Appendix.Table VIII shows the parameters used for experimentation.Results for two cases are presented, Case-A: 100-V dc-link voltage and 35-V line-to-line ac-side voltage and Case-B: 200-V dc-link voltage, 70-V line-to-line, and ac-side voltage.In both cases, the AFER is feeding the same resistive 50-load.These two cases are selected to show that the proposed control approach is suitable for different dc/ac voltage levels and for different current and power levels.Experimental results are shown in Fig. 10.Fig. 10(a) shows the experimental three-phase grid currents, where a balanced three-phase sinusoidal waveform is obtained.Only two currents are presented for the supply since the system is a 3ϕ balanced system.This allows the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.balances capacitor voltages.Finally, the experimental switch voltage stress is shown in Fig. 10(c), where each switch in the proposed B8 rectifier should withstand only half the dc-link To confirm the experimental results, Fig. 11(a) and (b) shows the corresponding simulation current waveforms using Table VIII parameters for the two selected experimental cases A and B, respectively.Good agreement between the experimental and simulation current waveforms using the same  times the power level in Case-A, Fig. 11(a).This is because the dc-side voltage level is doubled, and also, the ac-side voltage level is doubled (P = 3V I cos (ϕ) = (V 2 DC )/(R), assuming lossless system).However, the THD in both cases is the same.The reason is that the ac and dc voltage levels in Case-B are double that of Case-A, while the load resistance is the same.
To investigate the effect of increasing the power level by varying the load resistance while maintaining the same ac and dc voltage levels, Case-C is tested.Case-C utilizes the same parameters as Case-B, however with lower load resistance (25 ).Fig. 12(a) shows the simulation result for Case-C, where a 4.92% THD is recorded.This is expected as any increase in the load, while maintaining the same ac and dc voltage levels, results in a reduction in THD (see Fig. 2).
To investigate the effect of sampling time on THD, Case-D is examined, which uses exactly the same parameters as Case-C, however, with lower sampling time (20 µs).Reducing the sampling time (increasing the switching frequency) further improves the THD as shown in Fig. 12(b) (Case-D), where the reduction in sampling time results in a 2.89% THD in the simulation current waveform.

IX. CONCLUSION
This article presented an FCS-MPCC approach for an eight-switch two-leg NPC rectifier.In addition, two boost inductors instead of the conventional three inductors are utilized.A detailed mathematical model for the proposed B8 rectifier was presented in both the continuous and discrete-time domains.The problem of split dc-side capacitor imbalance is readily handled by modifying a cost function.The FCS-MPCC approach is illustrated for accurate reference current tracking.The comparison of the proposed control approach for the B8, two-inductor rectifier, against the conventional B4, three-inductor rectifier, with different control techniques was presented, showing the superior performance of the proposed B8 rectifier, where THD, switching, and conduction losses are reduced by 50%, 59%, and 14% respectively, at the same sampling time and with nearly the same average switching frequency.Although the proposed topology improves the rectifier performance with the same switch VA, extra gate drivers and clamping diodes are required increasing the cost, footprint, and complexity of the proposed topology.APPENDIX Fig. 13 shows the experimental test rig used for validation.
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Fig. 6 .
Fig. 6.Simulation results of the proposed FCS-MPCC B8 and HBCC B4 rectifiers.(a) Three-phase grid currents.(b) Reference and actual current of phase "a." (c) Voltage and current of phase "a."(d) Split dc-link capacitor voltage and output voltage.

Fig. 7 .
Fig. 7. Dynamic performance simulation results of the proposed FCS-MPCC B8 and HBCC B4 rectifiers.(a) Phase current.(b) Split dc-link capacitor voltage and output voltage.

Fig. 8 .
Fig. 8. Simulation results of the proposed converter under unbalanced and distorted grid voltage.(a) Three-phase grid voltage.(b) Unit template reference.(c) Three-phase grid current.(d) Split dc-link capacitor voltage and output voltage.

Fig. 9 .
Fig. 9. Simulation results of the B4, three-inductor rectifier with DB and MPCC.(a) Three-phase grid currents.(b) Split dc-link capacitor voltage and output voltage.

Fig. 11 .
Fig. 11.Simulation results using the experimental parameters given in Table VIII.(a) Case-A.(b) Case-B.

TABLE VIII RECTIFIER
PARAMETERS (EXPERIMENTAL)