Abstract
Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off.Firstly, this thesis investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation.
Based on the hop-count analysis, novel 3D heterogeneous NoC architectures are proposed to maximize the performance of NoCs with limited 3D routers, hence reducing power and area overheads.
In relation to improving the performance of heterogeneous 3D NoCs, several efficient routing schemes are proposed. Novel deadlock and livelock free deterministic, oblivious and adaptive routing algorithms are presented to consider the architectural dynamics of heterogeneous 3D NoCs and efficiently send packets along the limited interlayer links to reduce the average packet latency and energy consumption.
Furthermore to enhance design automation, a new systematic technique is proposed to automatically generate low latency heterogeneous architectures for a given application. The systematic approach efficiently assigns 3D routers to nodes that have high vertical link utilization and redistribute the router buffer sizes based on the buffer utilization of the architecture to improve the average packet latency and energy consumption.
With respect to application mapping and full system automation, this thesis proposes a new performance and energy-aware mapping scheme to balance traffic in NoCs while reducing the number of 3D routers in NoCs. The mapping tool efficiently exploits the application dynamics, assigns an optimized NoC size, maps the given applications to the NoC and generates a 3D NoC architecture with minimum number of 3D routers. Architectures generated by the proposed mapping scheme achieve lower average packet latency and energy consumption with a low design complexity compared to existing mapping schemes.
Finally, this thesis presents a fully automated user friendly framework for design and evaluation of 3D NoCs. The developed graphical user interface facilitates configuration of the evaluation framework to analyse the performance of various NoC features including routing algorithms, NoC dimensions and topologies of both homogeneous and heterogeneous architectures under synthetic and real world traffic patterns. Specifically, the framework can generate 3D NoC architectures with various router configurations, perform a pseudo cycle-accurate simulation and display a graphical representation of the performance results in real-time.
| Date of Award | 2014 |
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| Original language | English |
| Awarding Institution |
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| Supervisor | Ali Ahmadinia (Supervisor) & Alireza Shahrabi-Farahani (Supervisor) |