SystemC-based reconfigurable IP modelling for system-on-chip design

Ali Ahmadinia; Balal Ahmad; A. T. Erdogan; Tughrul Arslan

doi:10.1109/AHS.2008.63

SystemC-based reconfigurable IP modelling for system-on-chip design

Ali Ahmadinia, Balal Ahmad, A. T. Erdogan, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer'sA new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling.

Original language	English
Title of host publication	Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
Publisher	IEEE
ISBN (Print)	9780769531663
DOIs	https://doi.org/10.1109/AHS.2008.63
Publication status	Published - 1 Jan 2008

Keywords

system on chip design
engineering

Documents and Links

10.1109/AHS.2008.63

Cite this

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title = "SystemC-based reconfigurable IP modelling for system-on-chip design",

abstract = "A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer'sA new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling.",

keywords = "system on chip design, engineering",

author = "Ali Ahmadinia and Balal Ahmad and Erdogan, {A. T.} and Tughrul Arslan",

note = "<p>Paper presented at NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Noordwijk, The Netherlands, 22-25 June 2008. Proceedings ISBN: 9780769531663.</p>",

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doi = "10.1109/AHS.2008.63",

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AU - Ahmadinia, Ali

AU - Ahmad, Balal

AU - Erdogan, A. T.

AU - Arslan, Tughrul

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PY - 2008/1/1

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N2 - A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer'sA new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling.

AB - A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer'sA new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling.

KW - system on chip design

KW - engineering

U2 - 10.1109/AHS.2008.63

DO - 10.1109/AHS.2008.63

M3 - Conference contribution

SN - 9780769531663

BT - Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

PB - IEEE

ER -

SystemC-based reconfigurable IP modelling for system-on-chip design

Abstract

Keywords

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