Heterogeneous 3D network-on-chip architectures: area and power aware design techniques

Keyphrases

• Design Techniques 100%
• Network-on-chip Architectures 100%
• Energy-efficient Design 100%
• Three-dimensional Network-on-chip 100%
• 3D Network-on-chip (3D NoC) 100%
• Router 50%
• Router Architecture 50%
• System-on-chip 25%
• NoC Architecture 25%
• Efficient Power 25%
• On-chip Communication 25%
• Low Power 25%
• Performance Benefits 25%
• Next Generation Systems 25%
• Area-efficient 25%
• Heterogeneous NoC 25%
• Floorplanning 25%
• Efficient Architecture 25%
• Vertical Interconnect 25%

Computer Science

• Chip Architecture 100%
• Networks on Chips 100%
• Design Technique 100%
• Router Architecture 40%
• Vertical Interconnects 20%
• Communication Delay 20%
• Generation System 20%
• System-on-Chip 20%