Heterogeneous 3D network-on-chip architectures: area and power aware design techniques

Michael Opoku Agyeman, Ali Ahmadinia, Alireza Shahrabi-Farahani

    Research output: Contribution to journalArticle

    Abstract

    Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures.
    Original languageEnglish
    Number of pages24
    JournalJournal of Circuits, Systems and Computers
    Volume22
    Issue number4
    DOIs
    Publication statusPublished - Apr 2013

    Keywords

    • network-on-chip
    • 3D integration
    • low power design

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