FPGA low-power implementation of QRS detectors

Jovan Kovacevic, Radovan Stojanovic, Dejan Karadaglic, Bogdan Asanin, Zivorad Kovacevic, Zlatko Bundalo, Ferid Softic

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper presents a low power implementation of the
    algorithms for QRS complex detection in FPGA technology. We
    used cases of Balda and Pan-Tompkins algorithms for the case
    study. The optimization methodology is based on the use of
    heterogeneous logic blocks, pipelining, the variable code word
    lengths, on chip reorganizing of logic blocks and the control of
    the clocks. By applying the proposed techniques, the reduction of
    power consumption by 71% is achieved, in addition to the
    reduction of the chip occupancy by approx. 91%. The proposed
    optimization methodology and techniques are also applicable to
    other applications. The cases when the optimization could be
    justified in the term of project complexity are analysed and
    discussed.
    Original languageEnglish
    Title of host publication2014 3rd Mediterranean Conference on Embedded Computing (MECO)
    PublisherIEEE
    Pages98-101
    Number of pages4
    ISBN (Print)978-1-4799-4826-0
    DOIs
    Publication statusPublished - 2014

    Keywords

    • low power design
    • FPGA
    • QRS detection

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  • Cite this

    Kovacevic, J., Stojanovic, R., Karadaglic, D., Asanin, B., Kovacevic, Z., Bundalo, Z., & Softic, F. (2014). FPGA low-power implementation of QRS detectors. In 2014 3rd Mediterranean Conference on Embedded Computing (MECO) (pp. 98-101). IEEE. https://doi.org/10.1109/MECO.2014.6862667