FPGA low-power implementation of QRS detectors

Jovan Kovacevic; Radovan Stojanovic; Dejan Karadaglic; Bogdan Asanin; Zivorad Kovacevic; Zlatko Bundalo; Ferid Softic

doi:10.1109/MECO.2014.6862667

FPGA low-power implementation of QRS detectors

Jovan Kovacevic, Radovan Stojanovic, Dejan Karadaglic, Bogdan Asanin, Zivorad Kovacevic, Zlatko Bundalo, Ferid Softic

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a low power implementation of the
algorithms for QRS complex detection in FPGA technology. We
used cases of Balda and Pan-Tompkins algorithms for the case
study. The optimization methodology is based on the use of
heterogeneous logic blocks, pipelining, the variable code word
lengths, on chip reorganizing of logic blocks and the control of
the clocks. By applying the proposed techniques, the reduction of
power consumption by 71% is achieved, in addition to the
reduction of the chip occupancy by approx. 91%. The proposed
optimization methodology and techniques are also applicable to
other applications. The cases when the optimization could be
justified in the term of project complexity are analysed and
discussed.

Original language	English
Title of host publication	2014 3rd Mediterranean Conference on Embedded Computing (MECO)
Publisher	IEEE
Pages	98-101
Number of pages	4
ISBN (Print)	978-1-4799-4826-0
DOIs	https://doi.org/10.1109/MECO.2014.6862667
Publication status	Published - 2014

Keywords

low power design
FPGA
QRS detection

Documents and Links

10.1109/MECO.2014.6862667

http://ieeexplore.ieee.org.gcu.idm.oclc.org/xpl/articleDetails.jsp?tp=&arnumber=6862667&searchWithin%3Dp_Last_Names%3AKaradaglic%26matchBoolean%3Dtrue%26queryText%3D%28p_Authors%3AKaradaglic%29

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Cite this

Kovacevic, J., Stojanovic, R., Karadaglic, D., Asanin, B., Kovacevic, Z., Bundalo, Z., & Softic, F. (2014). FPGA low-power implementation of QRS detectors. In 2014 3rd Mediterranean Conference on Embedded Computing (MECO) (pp. 98-101). IEEE. https://doi.org/10.1109/MECO.2014.6862667

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title = "FPGA low-power implementation of QRS detectors",

abstract = "This paper presents a low power implementation of the algorithms for QRS complex detection in FPGA technology. We used cases of Balda and Pan-Tompkins algorithms for the case study. The optimization methodology is based on the use of heterogeneous logic blocks, pipelining, the variable code word lengths, on chip reorganizing of logic blocks and the control of the clocks. By applying the proposed techniques, the reduction of power consumption by 71% is achieved, in addition to the reduction of the chip occupancy by approx. 91%. The proposed optimization methodology and techniques are also applicable to other applications. The cases when the optimization could be justified in the term of project complexity are analysed and discussed.",

keywords = "low power design, FPGA, QRS detection",

author = "Jovan Kovacevic and Radovan Stojanovic and Dejan Karadaglic and Bogdan Asanin and Zivorad Kovacevic and Zlatko Bundalo and Ferid Softic",

year = "2014",

doi = "10.1109/MECO.2014.6862667",

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T1 - FPGA low-power implementation of QRS detectors

AU - Kovacevic, Jovan

AU - Stojanovic, Radovan

AU - Karadaglic, Dejan

AU - Asanin, Bogdan

AU - Kovacevic, Zivorad

AU - Bundalo, Zlatko

AU - Softic, Ferid

PY - 2014

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N2 - This paper presents a low power implementation of the algorithms for QRS complex detection in FPGA technology. We used cases of Balda and Pan-Tompkins algorithms for the case study. The optimization methodology is based on the use of heterogeneous logic blocks, pipelining, the variable code word lengths, on chip reorganizing of logic blocks and the control of the clocks. By applying the proposed techniques, the reduction of power consumption by 71% is achieved, in addition to the reduction of the chip occupancy by approx. 91%. The proposed optimization methodology and techniques are also applicable to other applications. The cases when the optimization could be justified in the term of project complexity are analysed and discussed.

AB - This paper presents a low power implementation of the algorithms for QRS complex detection in FPGA technology. We used cases of Balda and Pan-Tompkins algorithms for the case study. The optimization methodology is based on the use of heterogeneous logic blocks, pipelining, the variable code word lengths, on chip reorganizing of logic blocks and the control of the clocks. By applying the proposed techniques, the reduction of power consumption by 71% is achieved, in addition to the reduction of the chip occupancy by approx. 91%. The proposed optimization methodology and techniques are also applicable to other applications. The cases when the optimization could be justified in the term of project complexity are analysed and discussed.

KW - low power design

KW - FPGA

KW - QRS detection

U2 - 10.1109/MECO.2014.6862667

DO - 10.1109/MECO.2014.6862667

M3 - Conference contribution

SN - 978-1-4799-4826-0

SP - 98

EP - 101

BT - 2014 3rd Mediterranean Conference on Embedded Computing (MECO)

PB - IEEE

ER -