Abstract
This paper presents a low power implementation of the
algorithms for QRS complex detection in FPGA technology. We
used cases of Balda and Pan-Tompkins algorithms for the case
study. The optimization methodology is based on the use of
heterogeneous logic blocks, pipelining, the variable code word
lengths, on chip reorganizing of logic blocks and the control of
the clocks. By applying the proposed techniques, the reduction of
power consumption by 71% is achieved, in addition to the
reduction of the chip occupancy by approx. 91%. The proposed
optimization methodology and techniques are also applicable to
other applications. The cases when the optimization could be
justified in the term of project complexity are analysed and
discussed.
algorithms for QRS complex detection in FPGA technology. We
used cases of Balda and Pan-Tompkins algorithms for the case
study. The optimization methodology is based on the use of
heterogeneous logic blocks, pipelining, the variable code word
lengths, on chip reorganizing of logic blocks and the control of
the clocks. By applying the proposed techniques, the reduction of
power consumption by 71% is achieved, in addition to the
reduction of the chip occupancy by approx. 91%. The proposed
optimization methodology and techniques are also applicable to
other applications. The cases when the optimization could be
justified in the term of project complexity are analysed and
discussed.
| Original language | English |
|---|---|
| Title of host publication | 2014 3rd Mediterranean Conference on Embedded Computing (MECO) |
| Publisher | IEEE |
| Pages | 98-101 |
| Number of pages | 4 |
| ISBN (Print) | 978-1-4799-4826-0 |
| DOIs | |
| Publication status | Published - 2014 |
Keywords
- low power design
- FPGA
- QRS detection