Enabling dynamic communication for runtime circuit relocation

Adewale Adetomi*, Godwin Enemali, Tughrul Arslan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Runtime circuit relocation has been proposed for mitigating the effect of permanent damages in reconfigurable hardware, such as field-programmable gate arrays (FPGAs), with potentials to improve reliability and reduce or eliminate system downtime. However, a major obstacle to the adoption of circuit relocation is the presence of static communication links between the circuits. Existing solutions to this are either computationally expensive or counterintuitive to system reliability. This article proposes a dynamic communication mechanism that is able to circumvent the static links. The clock buffers in a typical FPGA use independent wires and, thus, do not constitute static routing. These are repurposed as network links to provide dynamic communication for relocatable circuits, with a demonstrator based on a four-node star network showing a bandwidth of 428.58 Mb/s for a 32-bit payload at an overhead of only 144 slices on a seven-series FPGA.
Original languageEnglish
Pages (from-to)142-155
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number1
Early online date30 Aug 2019
Publication statusPublished - Jan 2020


  • circuit relocation
  • network-on-chip
  • reconfigurable computing
  • reliability
  • network-on-chip (NoC)

ASJC Scopus subject areas

  • Software
  • Electrical and Electronic Engineering
  • Hardware and Architecture


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