Efficient routing techniques in heterogeneous 3D Networks-on-Chip

Michael Opoku Agyeman, Ali Ahmadinia, Alireza Shahrabi-Farahani

    Research output: Contribution to journalArticle

    Abstract

    Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs.
    Original languageEnglish
    Pages (from-to)389-407
    Number of pages19
    JournalInternational Journal of Parallel Computing
    Volume39
    Issue number9
    DOIs
    Publication statusPublished - Sep 2013

    Fingerprint

    Router
    Routers
    Routing
    Silicon
    Chip
    Manufacturing
    Topology
    Traffic
    Data storage equipment
    Three-dimensional
    Network on chip
    Network-on-chip
    Communication
    Architecture

    Keywords

    • NoC architecture
    • Network-on-Chip
    • router

    Cite this

    Agyeman, M. O., Ahmadinia, A., & Shahrabi-Farahani, A. (2013). Efficient routing techniques in heterogeneous 3D Networks-on-Chip. International Journal of Parallel Computing, 39(9), 389-407. https://doi.org/10.1016/j.parco.2013.04.009
    Agyeman, Michael Opoku ; Ahmadinia, Ali ; Shahrabi-Farahani, Alireza. / Efficient routing techniques in heterogeneous 3D Networks-on-Chip. In: International Journal of Parallel Computing. 2013 ; Vol. 39, No. 9. pp. 389-407.
    @article{dd9c12783b364b5a8d6a70903e31fef4,
    title = "Efficient routing techniques in heterogeneous 3D Networks-on-Chip",
    abstract = "Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs.",
    keywords = "NoC architecture, Network-on-Chip, router",
    author = "Agyeman, {Michael Opoku} and Ali Ahmadinia and Alireza Shahrabi-Farahani",
    note = "DOI corrected for REF valdiation by JM 20 Nov 2013",
    year = "2013",
    month = "9",
    doi = "10.1016/j.parco.2013.04.009",
    language = "English",
    volume = "39",
    pages = "389--407",
    number = "9",

    }

    Agyeman, MO, Ahmadinia, A & Shahrabi-Farahani, A 2013, 'Efficient routing techniques in heterogeneous 3D Networks-on-Chip', International Journal of Parallel Computing, vol. 39, no. 9, pp. 389-407. https://doi.org/10.1016/j.parco.2013.04.009

    Efficient routing techniques in heterogeneous 3D Networks-on-Chip. / Agyeman, Michael Opoku; Ahmadinia, Ali; Shahrabi-Farahani, Alireza.

    In: International Journal of Parallel Computing, Vol. 39, No. 9, 09.2013, p. 389-407.

    Research output: Contribution to journalArticle

    TY - JOUR

    T1 - Efficient routing techniques in heterogeneous 3D Networks-on-Chip

    AU - Agyeman, Michael Opoku

    AU - Ahmadinia, Ali

    AU - Shahrabi-Farahani, Alireza

    N1 - DOI corrected for REF valdiation by JM 20 Nov 2013

    PY - 2013/9

    Y1 - 2013/9

    N2 - Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs.

    AB - Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs.

    KW - NoC architecture

    KW - Network-on-Chip

    KW - router

    UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-84885384838&partnerID=8YFLogxK

    U2 - 10.1016/j.parco.2013.04.009

    DO - 10.1016/j.parco.2013.04.009

    M3 - Article

    VL - 39

    SP - 389

    EP - 407

    IS - 9

    ER -

    Agyeman MO, Ahmadinia A, Shahrabi-Farahani A. Efficient routing techniques in heterogeneous 3D Networks-on-Chip. International Journal of Parallel Computing. 2013 Sep;39(9):389-407. https://doi.org/10.1016/j.parco.2013.04.009