TY - JOUR
T1 - Efficient routing techniques in heterogeneous 3D Networks-on-Chip
AU - Agyeman, Michael Opoku
AU - Ahmadinia, Ali
AU - Shahrabi-Farahani, Alireza
N1 - DOI corrected for REF valdiation by JM 20 Nov 2013
PY - 2013/9
Y1 - 2013/9
N2 - Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs.
AB - Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs.
KW - NoC architecture
KW - Network-on-Chip
KW - router
UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-84885384838&partnerID=8YFLogxK
U2 - 10.1016/j.parco.2013.04.009
DO - 10.1016/j.parco.2013.04.009
M3 - Article
VL - 39
SP - 389
EP - 407
JO - International Journal of Parallel Computing
JF - International Journal of Parallel Computing
SN - 0167-8191
IS - 9
ER -