Efficient routing techniques in heterogeneous 3D Networks-on-Chip

Michael Opoku Agyeman, Ali Ahmadinia, Alireza Shahrabi-Farahani

    Research output: Contribution to journalArticle

    Abstract

    Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs.
    Original languageEnglish
    Pages (from-to)389-407
    Number of pages19
    JournalInternational Journal of Parallel Computing
    Volume39
    Issue number9
    DOIs
    Publication statusPublished - Sep 2013

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    Keywords

    • NoC architecture
    • Network-on-Chip
    • router

    Cite this

    Agyeman, M. O., Ahmadinia, A., & Shahrabi-Farahani, A. (2013). Efficient routing techniques in heterogeneous 3D Networks-on-Chip. International Journal of Parallel Computing, 39(9), 389-407. https://doi.org/10.1016/j.parco.2013.04.009