Efficient FPGA implementation of high-throughput mixed radix multipath delay commutator FFT processor for MIMO-OFDM

Mohammed Dali*, Abderezak Guessoum, Ryan M. Gibson, Abbes Amira, Naeem Ramzan

*Corresponding author for this work

    Research output: Contribution to journalArticle

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    Abstract

    This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM). The architecture presented is a Mixed-Radix Multipath Delay Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture, while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency design presented allows enhancing system throughput without requiring additional parallel data paths common in other current approaches, the presented design can process two and four independent data streams in parallel and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated significant resource efficiency and high-throughput in comparison to relevant current approaches within literature. The proposed architecture designs were realized with Xilinx System Generator (XSG) and evaluated on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively.
    Original languageEnglish
    Pages (from-to)27-38
    Number of pages12
    JournalAdvances in Electrical and Computer Engineering
    Volume17
    Issue number1
    DOIs
    Publication statusPublished - 28 Feb 2017

    Keywords

    • computer engineering
    • architecture
    • high-throughput design

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