This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades.
- network on chip
- NoC architecture