Dynamically reconfigurable NoC with bus based interface for ease of integration and reduced design time

Balal Ahmad; Ali Ahmadinia; Tughrul Arslan

doi:10.1109/AHS.2008.38

Dynamically reconfigurable NoC with bus based interface for ease of integration and reduced design time

Balal Ahmad, Ali Ahmadinia, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades.

Original language	English
Title of host publication	Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
Publisher	IEEE
ISBN (Print)	9780769531663
DOIs	https://doi.org/10.1109/AHS.2008.38
Publication status	Published - 1 Jan 2008

Keywords

network on chip
integration
NoC architecture
engineering

Documents and Links

10.1109/AHS.2008.38

http://researchonline.gcu.ac.uk/sec/196

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Cite this

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title = "Dynamically reconfigurable NoC with bus based interface for ease of integration and reduced design time",

abstract = "This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades.",

keywords = "network on chip, integration, NoC architecture, engineering",

author = "Balal Ahmad and Ali Ahmadinia and Tughrul Arslan",

note = "<p>Paper presented at the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Noordwijk, The Netherlands, 22-25 June 2008. Proceedings ISBN: 9780769531663.</p>",

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AU - Ahmadinia, Ali

AU - Arslan, Tughrul

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N2 - This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades.

AB - This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades.

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KW - integration

KW - NoC architecture

KW - engineering

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BT - Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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