Dynamically reconfigurable NoC with bus based interface for ease of integration and reduced design time

Balal Ahmad, Ali Ahmadinia, Tughrul Arslan

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades.

    Original languageEnglish
    Title of host publicationProceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
    PublisherIEEE
    ISBN (Print)9780769531663
    DOIs
    Publication statusPublished - 1 Jan 2008

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    Keywords

    • network on chip
    • integration
    • NoC architecture
    • engineering

    Cite this

    Ahmad, B., Ahmadinia, A., & Arslan, T. (2008). Dynamically reconfigurable NoC with bus based interface for ease of integration and reduced design time. In Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS) IEEE. https://doi.org/10.1109/AHS.2008.38