To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard.
|Title of host publication||Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication|
|Publication status||Published - 1 Jan 2010|
- network on chip design
- computer engineering