Dynamically reconfigurable NoC for future heterogeneous multi-core architectures

Balal Ahmad, Ali Ahmadinia, Tughrul Arslan

    Research output: Chapter in Book/Report/Conference proceedingChapter (peer-reviewed)


    To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard.

    Original languageEnglish
    Title of host publicationDynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication
    PublisherIGI Global
    ISBN (Print)9781615208074
    Publication statusPublished - 1 Jan 2010


    • network on chip design
    • computer engineering
    • NoC


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