Dynamically reconfigurable NoC for future heterogeneous multi-core architectures

Balal Ahmad; Ali Ahmadinia; Tughrul Arslan

Dynamically reconfigurable NoC for future heterogeneous multi-core architectures

Balal Ahmad, Ali Ahmadinia, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceeding › Chapter (peer-reviewed)

Abstract

To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard.

Original language	English
Title of host publication	Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication
Publisher	IGI Global
ISBN (Print)	9781615208074
Publication status	Published - 1 Jan 2010

Keywords

network on chip design
computer engineering
NoC

Cite this

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title = "Dynamically reconfigurable NoC for future heterogeneous multi-core architectures",

abstract = "To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard.",

keywords = "network on chip design, computer engineering, NoC",

author = "Balal Ahmad and Ali Ahmadinia and Tughrul Arslan",

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AU - Ahmad, Balal

AU - Ahmadinia, Ali

AU - Arslan, Tughrul

N1 - <p>Published by IGI Global (2010), ISBN: 9781615208074 (<a href="http://www.igi-global.com/bookstore/chapter.aspx?TitleId=44228">http://www.igi-global.com/bookstore/chapter.aspx?TitleId=44228</a>). Edited by J. Shen and P. Hsiung.</p>

PY - 2010/1/1

Y1 - 2010/1/1

N2 - To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard.

AB - To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard.

KW - network on chip design

KW - computer engineering

KW - NoC

M3 - Chapter (peer-reviewed)

SN - 9781615208074

BT - Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication

PB - IGI Global

ER -

Dynamically reconfigurable NoC for future heterogeneous multi-core architectures

Abstract

Keywords

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