Code improvements towards implementing HEVC decoder

Adeel Israr; Sajid Nazir; Muhammad Kaleem

doi:10.1109/ICEEST.2018.8643307

Code improvements towards implementing HEVC decoder

Adeel Israr, Sajid Nazir, Muhammad Kaleem

Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Abstract

HEVC is the latest video coding standard achieving better compression as compared to previous standards but at a higher complexity. Many applications require fast and real-time decoding of compressed video for which Field Programmable Gate Array (FPGA) is one of the efficient options. In this paper we provide the code improvement and implementation of the computationally intensive HEVC decoder. We describe our investigation for the implementation of HEVC decoder on Visual C++ 2008 platform and present improvements to the code of HEVC decoder required prior to its conversion to a hardware description language. The results for decoding time are also provided.

Original language	English
Title of host publication	2018 3rd International Conference on Emerging Trends in Engineering, Sciences and Technology (ICEEST)
Publisher	IEEE
Number of pages	6
ISBN (Electronic)	9781538682494
ISBN (Print)	9781538682500
DOIs	https://doi.org/10.1109/ICEEST.2018.8643307
Publication status	Published - 18 Feb 2019
Event	2018 3rd International Conference on Emerging Trends in Engineering, Sciences and Technology - Karachi, Pakistan Duration: 21 Dec 2018 → 22 Dec 2018

Conference

Conference	2018 3rd International Conference on Emerging Trends in Engineering, Sciences and Technology
Abbreviated title	ICEEST 2018
Country/Territory	Pakistan
City	Karachi
Period	21/12/18 → 22/12/18

Keywords

video decoding , compression , HEVC decoder , complexity , software debugging

Documents and Links

10.1109/ICEEST.2018.8643307

Israr, A. et al (2019) Code improvements towards implementing HEVC decoder
Copyright © 2019 IEEE. This is a post-peer review, pre-copy edited version of the article and may differ slightly from the final published version of the work. This work is made available in line with the publisher policy. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
Author accepted manuscript, 117 KB

Cite this

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title = "Code improvements towards implementing HEVC decoder",

abstract = "HEVC is the latest video coding standard achieving better compression as compared to previous standards but at a higher complexity. Many applications require fast and real-time decoding of compressed video for which Field Programmable Gate Array (FPGA) is one of the efficient options. In this paper we provide the code improvement and implementation of the computationally intensive HEVC decoder. We describe our investigation for the implementation of HEVC decoder on Visual C++ 2008 platform and present improvements to the code of HEVC decoder required prior to its conversion to a hardware description language. The results for decoding time are also provided.",

keywords = "video decoding , compression , HEVC decoder , complexity , software debugging",

author = "Adeel Israr and Sajid Nazir and Muhammad Kaleem",

note = "Acceptance in SAN (note from author) AAM: no embargo; 2018 3rd International Conference on Emerging Trends in Engineering, Sciences and Technology, ICEEST 2018 ; Conference date: 21-12-2018 Through 22-12-2018",

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doi = "10.1109/ICEEST.2018.8643307",

language = "English",

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T1 - Code improvements towards implementing HEVC decoder

AU - Israr, Adeel

AU - Nazir, Sajid

AU - Kaleem, Muhammad

N1 - Acceptance in SAN (note from author) AAM: no embargo

PY - 2019/2/18

Y1 - 2019/2/18

N2 - HEVC is the latest video coding standard achieving better compression as compared to previous standards but at a higher complexity. Many applications require fast and real-time decoding of compressed video for which Field Programmable Gate Array (FPGA) is one of the efficient options. In this paper we provide the code improvement and implementation of the computationally intensive HEVC decoder. We describe our investigation for the implementation of HEVC decoder on Visual C++ 2008 platform and present improvements to the code of HEVC decoder required prior to its conversion to a hardware description language. The results for decoding time are also provided.

AB - HEVC is the latest video coding standard achieving better compression as compared to previous standards but at a higher complexity. Many applications require fast and real-time decoding of compressed video for which Field Programmable Gate Array (FPGA) is one of the efficient options. In this paper we provide the code improvement and implementation of the computationally intensive HEVC decoder. We describe our investigation for the implementation of HEVC decoder on Visual C++ 2008 platform and present improvements to the code of HEVC decoder required prior to its conversion to a hardware description language. The results for decoding time are also provided.

KW - video decoding , compression , HEVC decoder , complexity , software debugging

U2 - 10.1109/ICEEST.2018.8643307

DO - 10.1109/ICEEST.2018.8643307

M3 - Conference contribution

SN - 9781538682500

BT - 2018 3rd International Conference on Emerging Trends in Engineering, Sciences and Technology (ICEEST)

PB - IEEE

T2 - 2018 3rd International Conference on Emerging Trends in Engineering, Sciences and Technology

Y2 - 21 December 2018 through 22 December 2018

ER -

Code improvements towards implementing HEVC decoder

Abstract

Conference

Keywords

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