Clock buffers, nets, and trees for on-chip communication: a novel network access technique in FPGAs

Adewale Adetomi; Godwin Enemali; Tughrul Arslan

doi:10.1109/IPDPSW.2017.156

Clock buffers, nets, and trees for on-chip communication: a novel network access technique in FPGAs

Adewale Adetomi, Godwin Enemali, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present CELOC, a Clock-Enabled Low-Overhead Communication technique. It is a network access technique that uses the clock buffers of an FPGA as serial communication links in order to reduce the overhead contributed by the NoC links. This technique involves toggling the clock enables of clock buffers to transmit communication signals from one circuit to another. A demonstrator based on a Xilinx 7 series FPGA showed that a single link can achieve a bandwidth of 6.5 Gbps at 100 MHz.

Original language	English
Title of host publication	2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	219-222
Number of pages	4
ISBN (Electronic)	9781538634080
DOIs	https://doi.org/10.1109/IPDPSW.2017.156
Publication status	Published - 3 Jul 2017
Externally published	Yes
Event	31st IEEE International Parallel and Distributed Processing Symposium Workshops - Orlando, United States Duration: 29 May 2017 → 2 Jun 2017 Conference number: 31st

Publication series

Name	Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017

Conference

Conference	31st IEEE International Parallel and Distributed Processing Symposium Workshops
Abbreviated title	IPDPSW 2017
Country/Territory	United States
City	Orlando
Period	29/05/17 → 2/06/17

Keywords

CELOC
clock buffers
low overhead
network on chip
NoC link
on-chip communication

ASJC Scopus subject areas

Hardware and Architecture
Computer Networks and Communications
Information Systems

Documents and Links

10.1109/IPDPSW.2017.156

Cite this

Adetomi, A., Enemali, G., & Arslan, T. (2017). Clock buffers, nets, and trees for on-chip communication: a novel network access technique in FPGAs. In 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 219-222). Article 7965046 (Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPSW.2017.156

Adetomi, Adewale ; Enemali, Godwin ; Arslan, Tughrul. / Clock buffers, nets, and trees for on-chip communication: a novel network access technique in FPGAs. 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). Institute of Electrical and Electronics Engineers Inc., 2017. pp. 219-222 (Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017).

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abstract = "The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present CELOC, a Clock-Enabled Low-Overhead Communication technique. It is a network access technique that uses the clock buffers of an FPGA as serial communication links in order to reduce the overhead contributed by the NoC links. This technique involves toggling the clock enables of clock buffers to transmit communication signals from one circuit to another. A demonstrator based on a Xilinx 7 series FPGA showed that a single link can achieve a bandwidth of 6.5 Gbps at 100 MHz.",

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author = "Adewale Adetomi and Godwin Enemali and Tughrul Arslan",

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Adetomi, A, Enemali, G & Arslan, T 2017, Clock buffers, nets, and trees for on-chip communication: a novel network access technique in FPGAs. in 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)., 7965046, Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017, Institute of Electrical and Electronics Engineers Inc., pp. 219-222, 31st IEEE International Parallel and Distributed Processing Symposium Workshops, Orlando, United States, 29/05/17. https://doi.org/10.1109/IPDPSW.2017.156

Clock buffers, nets, and trees for on-chip communication: a novel network access technique in FPGAs. / Adetomi, Adewale; Enemali, Godwin; Arslan, Tughrul.
2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). Institute of Electrical and Electronics Engineers Inc., 2017. p. 219-222 7965046 (Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Adetomi A, Enemali G, Arslan T. Clock buffers, nets, and trees for on-chip communication: a novel network access technique in FPGAs. In 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). Institute of Electrical and Electronics Engineers Inc. 2017. p. 219-222. 7965046. (Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017). doi: 10.1109/IPDPSW.2017.156

Clock buffers, nets, and trees for on-chip communication: a novel network access technique in FPGAs

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Documents and Links

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Cite this