Analysis and hardware testing of cell capacitor discharge currents during DC faults in half-bridge modular multilevel converters

A.A. Aboushady, K.H. Ahmed, D. Jovcic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Abstract

This paper focuses on the behaviour of the cell capacitor discharge currents during DC faults in half-bridge modular multilevel converters. Active switches, not designed for fault conditions, are tripped to minimize discharge currents effect on the semiconductor switches. Two levels of device protection are commonly in place; driver level protection monitoring collector-emitter voltage and overcurrent protection with feedback measurement and control. However, unavoidable tripping delay times, arising from factors such as sensor lags, controller sampling delays and hardware propagation delays, impact transient current shape and hence affect the selection of semiconductor device ratings as well as arm inductance. Analytical expressions are obtained for current slew rate, peak transient current and resultant I2t for the cell capacitor discharge current taking into account such delays. The study is backed by experimental testing on discharge of a 900V MMC capacitor.
Original languageEnglish
Title of host publication11th IET International Conference on AC and DC Power Transmission (ACDC) 2015
Publisher Institution of Engineering and Technology (IET)
Number of pages7
ISBN (Print)978-1-84919-982-7
DOIs
Publication statusPublished - 13 Jul 2015

Keywords

  • semiconductor switches
  • delays
  • electrical faults
  • overcurrent prtotection
  • power convertors

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    Aboushady, A. A., Ahmed, K. H., & Jovcic, D. (2015). Analysis and hardware testing of cell capacitor discharge currents during DC faults in half-bridge modular multilevel converters. In 11th IET International Conference on AC and DC Power Transmission (ACDC) 2015 Institution of Engineering and Technology (IET). https://doi.org/10.1049/cp.2015.0010