This paper presents a Single-path Delay Feedback (SDF) architecture for implementing a Fast Fourier Transform (FFT) processor on FPGA for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing. An FPGA resource efficient and shared multiplier technique for parallel processing of two and four data streams is demonstrated and utilized for realization within the presented SDF architecture based on a radix-2 butterfly model. The presented approach allows significant utilization efficiency of FPGA hardware-based multiplier elements opposed to a relative 50% less efficiency within conventional radix-2 SDF FPGA implemented techniques. The FPGA implementation demonstrated significant FPGA space resource savings compared to conventional radix-2 SDF methods and has been evaluated with other relative hardware architecture techniques. Additionally, the presented architecture is suitable for implementing and scaling to any FFT size N in correspondence with N = 2 m . Furthermore, the proposed architecture is easily controlled through binary counter control signals. The presented architectures have been designed with Xilinx System Generator, realized and evaluated on a Virtex-5 FPGA XC5VSX240T-2FF1738 device.
- field programmable gate arrays
- table lookup
- read only memory