An analytical performance model for the Spidergon NoC with virtual channels

Mahmoud Moadeli, Ali Shahrabi, Wim Vanderbauwhede, Partha Maji

    Research output: Contribution to journalArticle

    Abstract

    The Spidergon Network-on-Chip (NoC) was proposed to address the demand for a fixed and optimized communication infrastructure for cost-effective multi-processor Systems-on-Chip (MPSoC) development. To deal with the increasing diversity in quality of service requirements of SoC applications, the performance of this architecture needs to be improved. Virtual channels have traditionally been employed to enhance the performance of the interconnect networks. In this paper, we present analytical models to evaluate the message latency and network throughput in the Spidergon NoC and investigate the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions. Moreover an FPGA implementation of the Spidergon has been developed to provide an accurate analysis of the cost of employing virtual channels in this architecture.

    Original languageEnglish
    Pages (from-to)16-26
    Number of pages11
    JournalJournal of Systems Architecture
    Volume56
    Issue number1
    DOIs
    Publication statusPublished - 1 Jan 2010

    Keywords

    • network-on-Chip
    • performance modelling
    • spidergon
    • virtual channels

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