An analytical performance model for the spidergon NoC

Mahmoud Moadeli*, Ali Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

54 Citations (Scopus)

Abstract

Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discrete- event simulator.

Original languageEnglish
Title of host publication21st International Conference on Advanced Information Networking and Applications (AINA '07)
PublisherIEEE
Number of pages8
ISBN (Electronic)9781509087174
ISBN (Print)9780769528465
DOIs
Publication statusPublished - 4 Jun 2007

Publication series

Name
ISSN (Print)1550-445X
ISSN (Electronic)2332-5658

ASJC Scopus subject areas

  • General Engineering

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