An analytical comparison of the spidergon and rectangular mesh NoCs

Mahmoud Moadeli, Ali Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua

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    Abstract

    Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.

    Original languageEnglish
    Pages (from-to)167-188
    Number of pages22
    JournalJournal of Interconnection Networks
    Volume10
    Issue number1-2
    DOIs
    Publication statusPublished - 1 Jan 2009

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    Keywords

    • network on-chip
    • spidergon
    • performance model
    • rectangular mesh

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