Adaptive router architecture for optimising quality of service in networks-on-chip

Ali Ahmadinia; Ali Shahrabi

doi:10.1109/CIT.2010.311

Adaptive router architecture for optimising quality of service in networks-on-chip

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.

Original language	English
Title of host publication	Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT)
Publisher	IEEE
ISBN (Print)	9781424475476
DOIs	https://doi.org/10.1109/CIT.2010.311
Publication status	Published - 1 Jan 2010
Event	10th IEEE International Conference on Computer and Information Technology - Bradford, United Kingdom Duration: 29 Jun 2010 → 1 Jul 2010

Conference

Conference	10th IEEE International Conference on Computer and Information Technology
Abbreviated title	CIT 2010
Country/Territory	United Kingdom
City	Bradford
Period	29/06/10 → 1/07/10

Keywords

reconfigurable systems
networks on chip
router architecture
engineering

Documents and Links

10.1109/CIT.2010.311

Cite this

@inproceedings{f396c55688454003afb80ddfce47f6ee,

title = "Adaptive router architecture for optimising quality of service in networks-on-chip",

abstract = "Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.",

keywords = "reconfigurable systems, networks on chip, router architecture, engineering",

author = "Ali Ahmadinia and Ali Shahrabi",

note = "<p>Paper presented at the IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, UK, June 29 - July 1 2010. Proceedings ISBN: 9781424475476.</p>; 10th IEEE International Conference on Computer and Information Technology, CIT 2010 ; Conference date: 29-06-2010 Through 01-07-2010",

year = "2010",

month = jan,

day = "1",

doi = "10.1109/CIT.2010.311",

language = "English",

isbn = "9781424475476",

booktitle = "Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT)",

publisher = "IEEE",

}

Ahmadinia, A & Shahrabi, A 2010, Adaptive router architecture for optimising quality of service in networks-on-chip. in Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT). IEEE, 10th IEEE International Conference on Computer and Information Technology, Bradford, United Kingdom, 29/06/10. https://doi.org/10.1109/CIT.2010.311

TY - GEN

T1 - Adaptive router architecture for optimising quality of service in networks-on-chip

AU - Ahmadinia, Ali

AU - Shahrabi, Ali

N1 - <p>Paper presented at the IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, UK, June 29 - July 1 2010. Proceedings ISBN: 9781424475476.</p>

PY - 2010/1/1

Y1 - 2010/1/1

N2 - Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.

AB - Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.

KW - reconfigurable systems

KW - networks on chip

KW - router architecture

KW - engineering

U2 - 10.1109/CIT.2010.311

DO - 10.1109/CIT.2010.311

M3 - Conference contribution

SN - 9781424475476

BT - Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT)

PB - IEEE

T2 - 10th IEEE International Conference on Computer and Information Technology

Y2 - 29 June 2010 through 1 July 2010

ER -

Adaptive router architecture for optimising quality of service in networks-on-chip

Abstract

Conference

Keywords

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