Adaptive router architecture for optimising quality of service in networks-on-chip

Ali Ahmadinia, Ali Shahrabi

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.

    Original languageEnglish
    Title of host publicationProceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT)
    PublisherIEEE
    ISBN (Print)9781424475476
    DOIs
    Publication statusPublished - 1 Jan 2010

    Fingerprint

    Routers
    Quality of service
    Hardware
    Communication
    Network-on-chip

    Keywords

    • reconfigurable systems
    • networks on chip
    • router architecture
    • engineering

    Cite this

    Ahmadinia, A., & Shahrabi, A. (2010). Adaptive router architecture for optimising quality of service in networks-on-chip. In Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT) IEEE. https://doi.org/10.1109/CIT.2010.311
    Ahmadinia, Ali ; Shahrabi, Ali. / Adaptive router architecture for optimising quality of service in networks-on-chip. Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT). IEEE, 2010.
    @inproceedings{f396c55688454003afb80ddfce47f6ee,
    title = "Adaptive router architecture for optimising quality of service in networks-on-chip",
    abstract = "Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.",
    keywords = "reconfigurable systems, networks on chip, router architecture, engineering",
    author = "Ali Ahmadinia and Ali Shahrabi",
    note = "<p>Paper presented at the IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, UK, June 29 - July 1 2010. Proceedings ISBN: 9781424475476.</p>",
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    Ahmadinia, A & Shahrabi, A 2010, Adaptive router architecture for optimising quality of service in networks-on-chip. in Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT). IEEE. https://doi.org/10.1109/CIT.2010.311

    Adaptive router architecture for optimising quality of service in networks-on-chip. / Ahmadinia, Ali; Shahrabi, Ali.

    Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT). IEEE, 2010.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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    N2 - Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.

    AB - Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.

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    KW - engineering

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    Ahmadinia A, Shahrabi A. Adaptive router architecture for optimising quality of service in networks-on-chip. In Proceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT). IEEE. 2010 https://doi.org/10.1109/CIT.2010.311