Adaptive router architecture for optimising quality of service in networks-on-chip

Ali Ahmadinia, Ali Shahrabi

    Research output: Chapter in Book/Report/Conference proceedingConference contribution


    Networks-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed which can be used by all input channels in the router.

    Original languageEnglish
    Title of host publicationProceedings of the IEEE 10th International Conference on Computer and Information Technology (CIT)
    ISBN (Print)9781424475476
    Publication statusPublished - 1 Jan 2010


    • reconfigurable systems
    • networks on chip
    • router architecture
    • engineering


    Dive into the research topics of 'Adaptive router architecture for optimising quality of service in networks-on-chip'. Together they form a unique fingerprint.

    Cite this