Abstract
This paper presents a new system level power estimation methodology based on transaction level modeling for costum reconfigurable cores. The methodology can lead to significant improvement in trade-off between accuracy and efficiency of power estimation at system level. A SystemC based simulation environment is presented that allows rapid introduction of a power model into the executable specification of a sophisticated reconfigurable hardware design.
Original language | English |
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Title of host publication | Proceedings of the International Symposium on System-on-Chip (SoC) |
Publisher | IEEE |
ISBN (Print) | 9781424425419 |
DOIs | |
Publication status | Published - 1 Jan 2008 |
Keywords
- power estimation methodology
- reconfigurable systems
- engineering