A state based framework for efficient system-level power estimation of of costum reconfigurable cores

Ali Ahmadinia, Balal Ahmad, Tughrul Arslan

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    Abstract

    This paper presents a new system level power estimation methodology based on transaction level modeling for costum reconfigurable cores. The methodology can lead to significant improvement in trade-off between accuracy and efficiency of power estimation at system level. A SystemC based simulation environment is presented that allows rapid introduction of a power model into the executable specification of a sophisticated reconfigurable hardware design.

    Original languageEnglish
    Title of host publicationProceedings of the International Symposium on System-on-Chip (SoC)
    PublisherIEEE
    ISBN (Print)9781424425419
    DOIs
    Publication statusPublished - 1 Jan 2008

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    Reconfigurable hardware
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    Keywords

    • power estimation methodology
    • reconfigurable systems
    • engineering

    Cite this

    Ahmadinia, A., Ahmad, B., & Arslan, T. (2008). A state based framework for efficient system-level power estimation of of costum reconfigurable cores. In Proceedings of the International Symposium on System-on-Chip (SoC) IEEE. https://doi.org/10.1109/ISSOC.2008.4694889
    Ahmadinia, Ali ; Ahmad, Balal ; Arslan, Tughrul. / A state based framework for efficient system-level power estimation of of costum reconfigurable cores. Proceedings of the International Symposium on System-on-Chip (SoC). IEEE, 2008.
    @inproceedings{849c3dc657384031b6f48adb19d2bc87,
    title = "A state based framework for efficient system-level power estimation of of costum reconfigurable cores",
    abstract = "This paper presents a new system level power estimation methodology based on transaction level modeling for costum reconfigurable cores. The methodology can lead to significant improvement in trade-off between accuracy and efficiency of power estimation at system level. A SystemC based simulation environment is presented that allows rapid introduction of a power model into the executable specification of a sophisticated reconfigurable hardware design.",
    keywords = "power estimation methodology, reconfigurable systems, engineering",
    author = "Ali Ahmadinia and Balal Ahmad and Tughrul Arslan",
    note = "<p>Paper presented at the International Symposium on System-on-Chip (SoC), Tampere, Florida, 5-6 November 2008. Proceedings ISBN: 9781424425419.</p>",
    year = "2008",
    month = "1",
    day = "1",
    doi = "10.1109/ISSOC.2008.4694889",
    language = "English",
    isbn = "9781424425419",
    booktitle = "Proceedings of the International Symposium on System-on-Chip (SoC)",
    publisher = "IEEE",

    }

    Ahmadinia, A, Ahmad, B & Arslan, T 2008, A state based framework for efficient system-level power estimation of of costum reconfigurable cores. in Proceedings of the International Symposium on System-on-Chip (SoC). IEEE. https://doi.org/10.1109/ISSOC.2008.4694889

    A state based framework for efficient system-level power estimation of of costum reconfigurable cores. / Ahmadinia, Ali; Ahmad, Balal; Arslan, Tughrul.

    Proceedings of the International Symposium on System-on-Chip (SoC). IEEE, 2008.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

    TY - GEN

    T1 - A state based framework for efficient system-level power estimation of of costum reconfigurable cores

    AU - Ahmadinia, Ali

    AU - Ahmad, Balal

    AU - Arslan, Tughrul

    N1 - <p>Paper presented at the International Symposium on System-on-Chip (SoC), Tampere, Florida, 5-6 November 2008. Proceedings ISBN: 9781424425419.</p>

    PY - 2008/1/1

    Y1 - 2008/1/1

    N2 - This paper presents a new system level power estimation methodology based on transaction level modeling for costum reconfigurable cores. The methodology can lead to significant improvement in trade-off between accuracy and efficiency of power estimation at system level. A SystemC based simulation environment is presented that allows rapid introduction of a power model into the executable specification of a sophisticated reconfigurable hardware design.

    AB - This paper presents a new system level power estimation methodology based on transaction level modeling for costum reconfigurable cores. The methodology can lead to significant improvement in trade-off between accuracy and efficiency of power estimation at system level. A SystemC based simulation environment is presented that allows rapid introduction of a power model into the executable specification of a sophisticated reconfigurable hardware design.

    KW - power estimation methodology

    KW - reconfigurable systems

    KW - engineering

    U2 - 10.1109/ISSOC.2008.4694889

    DO - 10.1109/ISSOC.2008.4694889

    M3 - Conference contribution

    SN - 9781424425419

    BT - Proceedings of the International Symposium on System-on-Chip (SoC)

    PB - IEEE

    ER -

    Ahmadinia A, Ahmad B, Arslan T. A state based framework for efficient system-level power estimation of of costum reconfigurable cores. In Proceedings of the International Symposium on System-on-Chip (SoC). IEEE. 2008 https://doi.org/10.1109/ISSOC.2008.4694889

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