A single chip system for ECG feature extraction

Sasa Knezevic; Radovan Stojanovic; Dejan Karadaglic; Bogdan Asanin

doi:10.1109/MECO.2013.6601325

A single chip system for ECG feature extraction

Sasa Knezevic, Radovan Stojanovic, Dejan Karadaglic, Bogdan Asanin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

190 Downloads (Pure)

Abstract

This paper proposes an on-line system for feature extraction from ECG signal. The QRS detector, RR interval calculator, heart rate calculator and additional modules are developed in VHDL code and embedded in a single FPGA chip. The overall design has a low hardware occupation, 1838 LEs, and minimal number of setting parameters, only two, sampling and clock rates. The achieved accuracy is 97.5%. As such, it is very suitable for embedding in wearable health care systems, portable instruments and telemedicine devices. The methodology for QRS detection, system architecture and preliminary testing results are presented.

Original language	English
Title of host publication	Embedded Computing (MECO), 2013 2nd Mediterranean Conference on
Publisher	IEEE
Pages	88-92
Number of pages	5
ISBN (Print)	978-9940-9436-1-5
DOIs	https://doi.org/10.1109/MECO.2013.6601325
Publication status	Published - 2013

Keywords

FPGA
discrete wavelet transform
QRS complex
RR interval
heart rate detection

Documents and Links

10.1109/MECO.2013.6601325

Knezevic, S. et al (2013) A single chip system for ecg feature extraction
This is the accepted author manuscript of a conference paper published by IEEE. Available at: http://ieeexplore.ieee.org/document/6601325/ © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Author accepted manuscript, 1.88 MB

http://ieeexplore.ieee.org.gcu.idm.oclc.org/xpl/articleDetails.jsp?arnumber=6601325

Cite this

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title = "A single chip system for ECG feature extraction",

abstract = "This paper proposes an on-line system for feature extraction from ECG signal. The QRS detector, RR interval calculator, heart rate calculator and additional modules are developed in VHDL code and embedded in a single FPGA chip. The overall design has a low hardware occupation, 1838 LEs, and minimal number of setting parameters, only two, sampling and clock rates. The achieved accuracy is 97.5%. As such, it is very suitable for embedding in wearable health care systems, portable instruments and telemedicine devices. The methodology for QRS detection, system architecture and preliminary testing results are presented. ",

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author = "Sasa Knezevic and Radovan Stojanovic and Dejan Karadaglic and Bogdan Asanin",

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doi = "10.1109/MECO.2013.6601325",

language = "English",

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AU - Knezevic, Sasa

AU - Stojanovic, Radovan

AU - Karadaglic, Dejan

AU - Asanin, Bogdan

PY - 2013

Y1 - 2013

N2 - This paper proposes an on-line system for feature extraction from ECG signal. The QRS detector, RR interval calculator, heart rate calculator and additional modules are developed in VHDL code and embedded in a single FPGA chip. The overall design has a low hardware occupation, 1838 LEs, and minimal number of setting parameters, only two, sampling and clock rates. The achieved accuracy is 97.5%. As such, it is very suitable for embedding in wearable health care systems, portable instruments and telemedicine devices. The methodology for QRS detection, system architecture and preliminary testing results are presented.

AB - This paper proposes an on-line system for feature extraction from ECG signal. The QRS detector, RR interval calculator, heart rate calculator and additional modules are developed in VHDL code and embedded in a single FPGA chip. The overall design has a low hardware occupation, 1838 LEs, and minimal number of setting parameters, only two, sampling and clock rates. The achieved accuracy is 97.5%. As such, it is very suitable for embedding in wearable health care systems, portable instruments and telemedicine devices. The methodology for QRS detection, system architecture and preliminary testing results are presented.

KW - FPGA

KW - discrete wavelet transform

KW - QRS complex

KW - RR interval

KW - heart rate detection

U2 - 10.1109/MECO.2013.6601325

DO - 10.1109/MECO.2013.6601325

M3 - Conference contribution

SN - 978-9940-9436-1-5

SP - 88

EP - 92

BT - Embedded Computing (MECO), 2013 2nd Mediterranean Conference on

PB - IEEE

ER -

A single chip system for ECG feature extraction

Abstract

Keywords

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