A highly adaptive and efficient router architecture for network-on-chip

Ali Ahmadinia, Ali Shahrabi

    Research output: Contribution to journalArticle

    Abstract

    Network-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. Efficient buffer management is not only instrumental in the overall performance of the on-chip networks but also greatly affects the network energy consumption. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed, which can be used by all input channels in the router.

    Original languageEnglish
    Pages (from-to)1295-1307
    Number of pages13
    JournalComputer Journal
    Volume54
    Issue number8
    Early online date10 Jan 2011
    DOIs
    Publication statusPublished - 2011

    Keywords

    • network-on-chip
    • router architecture
    • computer engineering
    • low power design

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