A functionality-based runtime relocation system for circuits on heterogeneous FPGAs

Godwin Enemali*, Adewale Adetomi, Gopalakrishnan Seetharaman, Tughrul Arslan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

Runtime relocation of circuits on field-programmable gate arrays (FPGAs) has been proposed for achieving many desirable features including fault tolerance, defragmentation, and system load balancing. However, the changes in the architectural composition of FPGAs have made relocation more challenging mainly because FPGAs have become more heterogeneous. Previous and state-of-the-art circuit relocation systems on FPGAs have relied only on direct bitstream relocation which requires the source and destination resource layouts to be the same, as well as access to the design bitstream for manipulation. Hence, their efficiency on modern heterogeneous chips greatly reduces, and mostly cannot be applied to encrypted bitstreams of intellectual property blocks. In this brief, we present a circuit relocator which augments direct bitstream relocation with a functionality-based relocation scheme. We demonstrate the feasibility of the proposed technique using a CORDIC application and show that an average of over 2.6-fold increase in the number of relocations can be obtained compared to only direct bitstream relocation at the expense of a small memory overhead and manageable relocation time for this case study.
Original languageEnglish
Pages (from-to)612-616
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume65
Issue number5
Early online date12 Apr 2018
DOIs
Publication statusPublished - May 2018

Keywords

  • Bitstream relocation
  • FPGA
  • reconfigurable hardware
  • look-up-table
  • heterogeneous

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